1. Field of the Invention
The present invention relates to a semiconductor memory of which a memory manufacturing process yield is improved.
2. Description of Related Art
In the manufacturing of a semiconductor memory such as a flash memory, defective memories are relieved to improve memory manufacturing process yields.
FIG. 18 is a view showing a conventional conception of the relief of a defective flash memory.
In a general method of relieving a defective memory, a spare bit line having a memory cell is prepared in advance in a spare area of a memory chip. When a defective memory cell occurs in a main area of the memory chip, a main bit line corresponding to the defective memory cell is replaced with the spare bit line having a memory cell.
FIG. 19 is a view showing the configuration of a conventional semiconductor memory. In FIG. 19, 1 indicates a memory cell array having a plurality of memory cells. 2 indicates a spare cell array having a memory cell. 3 indicates an X decoder for decoding lower address bits (or lower bits of an address). 4 indicates a Y decoder for decoding upper address bits (or upper bits of the address). 5 indicates a sense amplifier for reading out data of a memory cell from the memory cell array 1 or the spare cell array 2. 6 indicates a selector for outputting the data read out by the sense amplifier 5 to a data bus. 7 indicates a repair circuit.
Next, an operation of the conventional semiconductor memory will be described.
When an address of a desired memory cell is input to an address bus to read out desired data of the desired memory cell, upper bits of the address is received in the Y decoder 4 and is decoded to specify a word line corresponding to the desired memory cell of the memory cell array 1. Also, lower bits of the address is received in the X decoder 3 and is decoded to specify a bit line corresponding to the desired memory cell of the memory cell array 1. Thereafter, desired data of the desired memory cell placed at a crossing point of the word line specified by the Y decoder 4 and the bit line specified by the X decoder 3 is read out to the sense amplifier 5, and the desired data is output to the data bus through the selector 6.
The defective memory relieving method shown in FIG. 18 will be described in detail with reference to FIG. 20.
FIG. 20 is a view showing the configuration of an address replacing circuit. To simplify the description of the method, both a main area corresponding to addresses (or four memory cells) designated by 2 bits and a spare area corresponding to one bit line (or one memory cell) are prepared in advance.
A decoding circuit corresponding to the assigned addresses is connected to four main bit lines of the main area. For example, when an address AD[1:0]=10 is input to an address bus, the levels of main bit lines other than a specific main bit line corresponding to the address AD=10 are lowered to the GND level. Also, a decoding circuit having laser trimming (LT) fuses is connected to a spare bit line of the spare area. In cases where LT fuses of a spare memory cell are cut by a laser beam (or laser trimming is performed for LT fuses), one main bit line corresponding to any address is replaced with the spare bit line. In FIG. 20, because a memory cell of a main bit line corresponding to the address AD=10 is defective, LT fuses of a spare memory cell are cut, and the main bit line of the defective memory cell is replaced with the spare bit line.
FIG. 21 is an explanatory view showing a function of the selector 6 shown in FIG. 19.
As is described with reference to FIG. 20, in cases where an address is assigned to the spare bit line by cutting the LT fuses, both the spare bit line and the main bit line of the defective memory cell correspond to the same address. Therefore, one of both the spare bit line and the main bit line is selected in the selector 6. In a normal operation (or in case of no defective bit), data output from the main bit line is selected in the selector 6. However, in cases where data is output from the spare bit line (or in cases where a memory cell of a main bit line, to which an address assigned to the spare bit line is also assigned, is defective), data output from the spare bit line is selected in the selector 6.
However, because the conventional semiconductor memory has the above-described configuration, in cases where the number of main bit lines corresponding to defective memory cells exceeds the number of spare bit lines prepared in advance, it is impossible to relieve all the main bit lines corresponding to defective memory cells. Therefore, a problem has arisen that the yield for the semiconductor memory cannot be improved.
Also, there is a case where a read only memory (ROM) having a defective memory block is used as a ROM having no defective memory block. For example, even though it is impossible to relieve a semiconductor memory having a memory capacity of 256K bytes as a memory of 256K bytes (hereinafter, called 256 KB-memory), in cases where defective memory cells are concentrated at a narrow area, there is a possibility that the semiconductor memory can be relieved as a 128 KB-memory by setting a memory area of the other memory capacity of 128K bytes as a non-use memory area. However, the conventional semiconductor memory cannot be relieved as a 128 KB-memory.
An object of the present invention is to provide, with due consideration to the drawbacks of the conventional semiconductor memory, a semiconductor memory of which the yield is heightened.
The object is achieved by the provision of a semiconductor memory comprising a memory cell array having a plurality of memory blocks, identification information storing means for storing identification information which identifies a defective memory block existing in the memory blocks of the memory cell array, and address changing means for receiving an address from an address bus, changing the address to a changed address according to the identification information of the identification information storing means and outputting the changed address to a decoder of the memory cell array to specify a memory cell of the memory cell array according to the changed address.
In the above configuration, a predetermined address is changed to a physical address assigned to the defective memory block. Therefore, to relieve the semiconductor memory as a memory of a specific memory capacity lower than that of the semiconductor memory, a test suitable for the specific memory capacity can be easily performed for the memory having the blocks of the semiconductor memory other than the defective memory block of the predetermined address. Accordingly, the yield of the semiconductor memory can be improved.
It is preferred that a usable memory capacity of the memory cell array is stored in the identification information storing means.
Therefore, after a test suitable for the memory capacity of the semiconductor memory, a test suitable for the usable memory capacity determined to relive the semiconductor memory can be easily performed.
It is also preferred that the identification information storing means is arranged in an area of a programmable read-only memory.
Therefore, the yield of the semiconductor memory can be improved without influencing on a memory area used by a user.
It is also preferred that the identification information storing means is arranged in an area of a user read-only memory.
Therefore, the identification information can be easily stored in the identification information storing means.
It is also preferred that the identification information storing means is arranged in an area of a boot read-only memory.
Therefore, the identification information can be easily stored in the identification information storing means without influencing on a memory area used by a user.
It is also preferred that the identification information storing means has a fuse corresponding to each of the memory blocks of the memory cell array, and the fuse corresponding to the defective memory block is cut.
Therefore, the configuration of the identification information storing means can be simplified.
It is also preferred that the identification information stored in the identification information storing means is written on a chip of the semiconductor memory according to laser marking.
Therefore, an operator managing a test process can easily recognize the identification information.
It is also preferred that the address changing means comprises a logic circuit for receiving both an address signal indicating a value of an address bit of the address and a control signal controlling the address change, calculating an exclusive logical sum of both the address signal and the control signal and outputting the exclusive logical sum as the value of an address bit of the changed address.
Therefore, the address can be reliably changed without complicating the configuration of the address changing means.
It is also preferred that the address changing means comprises a control signal producing circuit having a fuse for outputting the control signal, which indicates no change of the address in case of a non-cut fuse, to the logic circuit and outputting the control signal, which indicates a change of the address in case of a cut fuse, to the logic circuit.
Therefore, the address change can be reliably controlled.
It is also preferred that the address changing means comprises a software tool so as to connect a plurality of memory blocks of the memory cell array other than the defective memory block according to a software process.
Therefore, the configuration of the address changing means can be simplified.
It is also preferred that the address change is performed by the address changing means so as to change a specific address assigned to a bottom memory block to a physical address of the defective memory block identified by the identification information.
Therefore, a test suitable for a memory capacity of memory blocks other than the defective memory block can be easily performed, and the yield of the semiconductor memory can be improved.